1. Technical Field
The present invention relates in general to data processing and more particularly to handling the processing of requests to deallocate a data cache block in a cache memory of a data processing system.
2. Description of the Related Art
A conventional multiprocessor (MP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, with each lower level generally having a successively longer access latency. Thus, a level one (L1) cache generally has a lower access latency than a level two (L2) cache, which in turn has a lower access latency than a level three (L3) cache.
To provide a balance between competing design considerations such as power dissipation, size, access latency and hit rates, many MP systems implement set-associative caches, which group cache entries in congruence classes each containing multiple entries for storing cache lines sharing a common address index. The removal (eviction) of cache lines from the entries in each congruence class is governed by a replacement policy, which is preferably selected to remove from the congruence class the cache line least likely to again be accessed. Common replacement policies include least-recently used (LRU) and round-robin.
For some workloads, the replacement policy implemented by the cache hardware is supplemented by additional software management of the cache(s). For example, in some cases, a programmer or compiler can insert explicit instructions in an application program to cause the cache hierarchy to invalidate particular cache lines or to flush particular cache lines to system memory. Examples of cache management instructions from the PowerPC instruction set architecture are listed in Table I below.
TABLE IPowerPC MnemonicInstruction nameDCBFFlush Data Cache LineDCBIInvalidate Data Cache LineDCBZZero Data Cache LineICBIInvalidate Instruction Cache Line
In some cases, explicit cache management instructions can cause inefficiency in execution of an application program, for example, by invalidating a cache line or flushing the cache line to system memory prior to the cache line being accessed again. In such cases, the access to the cache line following the software-managed invalidation or flush will incur significantly increased access latency as the cache line must again be retrieved from system memory, which may have an access latency that is two orders of magnitude greater than the upper levels of the cache hierarchy.